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4mb, sync lw, lvttl, rev 1.2 1 / 28 september 24, 1998 cxk77b3641agb / CXK77B1841AGB sony 33/37/5/6 4mb late write lvttl high speed synchronous srams (128k x 36 or 256k x 18 organization) preliminary description features r-r mode r-l, r-ft modes ? fast cycle / access time t khkh / t khqv t khkh / t khqv --------------------------------- ------------------ ------------------ -33 3.3ns / 2.3ns 5.0ns / 5.0ns -37 3.6ns / 2.4ns 5.3ns / 5.3ns -5 5.0ns / 2.5ns 5.3ns / 5.3ns -6 6.0ns / 2.5ns 6.0ns / 6.0ns ? single 3.3v power supply (v dd ): 3.3v 5% ? register - register (r-r), register - latch (r-l), or register - flow thru (r-ft) read operations ? read operation protocol selectable via dedicated mode pins (m1, m2) ? fully coherent, late write, self-timed write operations ? byte write capability ? differential input clocks (k/k ) ? asynchronous output enable (g ) ? dedicated output supply voltage (v ddq ): 2.5v or 3.3v typical ? lvttl/lvcmos-compatible i/o interface ? sleep (power down) mode via dedicated mode pin (zz) ? jtag boundary scan (subset of ieee standard 1149.1) ? 119 pin (7x17), 1.27mm pitch, 14mm x 22mm plastic ball grid array (pbga) package the cxk77b3641a (organized as 131,072 words by 36 bits) and the cxk77b1841a (organized as 262,144 words by 18 bits) are high speed bicmos synchronous static rams with common i/o pins. these synchronous srams integrate input registers, high speed ram, output registers/latches, and a one-deep write buffer onto a single monolithic ic. three distinct read operatio n protocols, register - register (r-r), register - latch (r-l), and register - flow thru (r-ft), and one write operation protocol , late write (lw), are supported, providing a flexible, high-performance user interface. all address, data, and control input signals except g (output enable) and zz (sleep mode) are registered on the positive edge of k clock. read operation protocol is selectable through external mode pins m1 and m2. write operations are internally self-timed, eliminating the need for complex off-chip write pulse generation. in register - lat ch and register - flow thru modes, when sw (global write enable) is driven active, the subsequent positive edge of k clock tri- states the srams output drivers immediately, allowing read-write-read operations to be initiated consecutively, with no dead cycles between them. sleep (power down) mode control is provided through the asynchronous zz input. 300 mhz operation is obtained from a single 3.3v power supply. jtag boundary scan interface is provided using a subset of ieee standard 1149.1 protocol.
4mb, sync lw, lvttl, rev 1.2 2 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary 128k x 36 pin assignment (top view) notes: 1. pad locations 2t and 6t are true no-connects. however, they are defined as sa address inputs in x18 lw srams. 2. pad location 6b is a true no-connect. however, it is defined as an sa address input in 8mb and 16mb lw srams. 3. pad location 2b is a true no-connect. however, it is defined as an sa address input in 16mb lw srams. 4. pad location 4d is a true no-connect. however, it is defined as a zq output impedance control resister input in hstl lw srams. 5. pad locations 3j and 5j are true no-connects. however, they are defined as v ref input reference voltage inputs in hstl lw srams. 1234567 a v ddq sa6 sa7 nc sa3 sa2 v ddq b nc nc (3) sa8 nc sa4 nc (2) nc c nc sa12 sa5 v dd sa0 sa13 nc d dq7c dq8c v ss nc (4) v ss dq8b dq7b e dq5c dq6c v ss ss v ss dq6b dq5b f v ddq dq4c v ss g v ss dq4b v ddq g dq2c dq3c sbw cc sbw b dq3b dq2b h dq0c dq1c v ss cv ss dq1b dq0b j v ddq v dd nc (5) v dd nc (5) v dd v ddq k dq0d dq1d v ss kv ss dq1a dq0a l dq2d dq3d sbw dk sbw a dq3a dq2a m v ddq dq4d v ss sw v ss dq4a v ddq n dq5d dq6d v ss sa14 v ss dq6a dq5a p dq7d dq8d v ss sa11 v ss dq8a dq7a r nc sa10 m1 v dd m2 sa15 nc t nc nc (1) sa9 sa16 sa1 nc (1) zz u v ddq tms tdi tck tdo nc v ddq
4mb, sync lw, lvttl, rev 1.2 3 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary 256k x 18 pin assignment (top view) notes: 1a. pad location 4t is a true no-connect. however, it is defined as an sa address input in x36 lw srams. 1b. pad locations 2d, 7d, 1e, 6e, 2f, 1g, 6g, 2h, 7h, 1k, 6k, 2l, 7l, 6m, 2n, 7n, 1p, and 6p are true no-connects. however, they are defined as dq data inputs / outputs in x36 lw srams. 2. pad location 6b is a true no-connect. however, it is defined as an sa address input in 8mb and 16mb lw srams. 3. pad location 2b is a true no-connect. however, it is defined as an sa address input in 16mb lw srams. 4. pad location 4d is a true no-connect. however, it is defined as a zq output impedance control resister input in hstl lw srams. 5. pad locations 3j and 5j are true no-connects. however, they are defined as v ref input reference voltage inputs in hstl lw srams. 1234567 a v ddq sa6 sa7 nc sa3 sa2 v ddq b nc nc (3) sa8 nc sa4 nc (2) nc c nc sa12 sa5 v dd sa0 sa13 nc d dq0b nc (1b) v ss nc (4) v ss dq8a nc (1b) e nc (1b) dq1b v ss ss v ss nc (1b) dq7a f v ddq nc (1b) v ss g v ss dq6a v ddq g nc (1b) dq2b sbw bc v ss nc (1b) dq5a h dq3b nc (1b) v ss cv ss dq4a nc (1b) j v ddq v dd nc (5) v dd nc (5) v dd v ddq k nc (1b) dq4b v ss kv ss nc (1b) dq3a l dq5b nc (1b) v ss k sbw a dq2a nc (1b) m v ddq dq6b v ss sw v ss nc (1b) v ddq n dq7b nc (1b) v ss sa14 v ss dq1a nc (1b) p nc (1b) dq8b v ss sa11 v ss nc (1b) dq0a r nc sa10 m1 v dd m2 sa15 nc t nc sa17 sa9 nc (1a) sa1 sa16 zz u v ddq tms tdi tck tdo nc v ddq
4mb, sync lw, lvttl, rev 1.2 4 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary pin description symbol type description sa input synchronous address inputs - registered on the rising edge of k. dqa, dqb dqc, dqd i/o synchronous data inputs / outputs - registered on the rising edge of k during write operations. dqa - indicates data byte a dqb - indicates data byte b dqc - indicates data byte c dqd - indicates data byte d k, k input differential input clocks c, c input differential output control clocks - reserved for future use. ss input synchronous select input - registered on the rising edge of k. ss = 0 specifies a write operation when sw = 0 specifies a read operation when sw = 1 ss = 1 specifies a deselect operation sw input synchronous global write enable input - registered on the rising edge of k. sw = 0 specifies a write operation when ss = 0 sw = 1 specifies a read operation when ss = 0 sbw a, sbw b, sbw c, sbw d input synchronous byte write enable inputs - registered on the rising edge of k. sbw a = 0 specifies write data byte a when ss = 0 and sw = 0 sbw b = 0 specifies write data byte b when ss = 0 and sw = 0 sbw c = 0 specifies write data byte c when ss = 0 and sw = 0 sbw d = 0 specifies write data byte d when ss = 0 and sw = 0 g input asynchronous output enable input - de-asserted (high) forces the data output drivers to hi-z. zz input asynchronous sleep mode input - asserted (high) forces the sram into low-power mode. m1, m2 input read operation protocol select - these mode pins must be tied to v dd or v ss before power-up. m1:m2 = 00 specifies register - flow thru read operations m1:m2 = 01 specifies register - register read operations m1:m2 = 10 specifies register - latch read operations m1:m2 = 11 reserved for future use v dd 3.3v core power supply - core supply voltage. v ddq output power supply - output buffer supply voltage. v ss ground tck input jtag clock tms input jtag mode select tdi input jtag data in tdo output jtag data out nc no connect - these pins are true no-connects, i.e. there is no internal chip connection to these pins. they can be left unconnected or tied directly to v dd or v ss .
4mb, sync lw, lvttl, rev 1.2 5 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary address write pulse 128k x 36 dout din 2:1 mux output latch reg. 2:1 mux reg. write store reg. read comp. reg. reg. reg. self time write logic output clock mode control sa ss sw sbw k/k m1 m2 g dq ^ ^ ^ ^ block diagram kint kint kint kint kint or 256k x 18 input clock
4mb, sync lw, lvttl, rev 1.2 6 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary ? tr uth tables register - register mode zz ss (t n ) sw (t n ) sbw x (t n ) g mode dq (t n ) dq (t n+1 ) v dd current h x x x x sleep (power down) mode hi - z hi - z i sb l h x x x deselect x hi - z i dd l l h x h read hi - z hi - z i dd l l h x l read x q(t n )i dd l l l l x write all bytes x d(t n )i dd l l l x x write bytes with sbw x = l x d(t n )i dd l l l h x abort write x hi - z i dd register - latch and register - flow thru mode zz ss (t n ) sw (t n ) sbw x (t n ) g mode dq (t n ) dq (t n+1 ) v dd current h x x x x sleep (power down) mode hi - z hi - z i sb l h x x x deselect hi - z x i dd l l h x h read hi - z hi - z i dd l l h x l read q(t n )x i dd l l l l x write all bytes hi - z d(t n )i dd l l l x x write bytes with sbw x = l hi - z d(t n )i dd l l l h x abort write hi - z x i dd
4mb, sync lw, lvttl, rev 1.2 7 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary ? read operations these devices support three distinct jedec standard read protocols via mode pins m1 and m2. the mode pins must be set during power-up, and cannot change during sram operation. mode select truth table . when a read operation is initiated, all address and control signals (except g and zz) are latched into input registers on the rising edge of k clock. the latched address is decoded and then used to access a particular location in the internal memory array. these two events occur regardless which read protocol is selected. after the memory location is accessed, the read protocol determines when data from that memory location is driven valid externally. register - register mode in register - register mode, data is driven valid externally from the subsequent rising edge of k clock, one full k clock cycle after the address is latched. data remains valid until at least the next rising edge of k clock, one full k clock cycle thereafter. register - latch mode in register - latch mode, data is driven valid externally from the subsequent falling edge of k clock, or, some minimum amount of time after the address is latched (determined by the access time of the mem- ory array), whichever is greater. data remains valid until at least the next falling edge of k clock, ap- proximately one full k clock cycle thereafter. register - flow thru mode in register - flow thru mode, data is driven valid immediately, some minimum amount of time after the address is latched (determined by the access time of the memory array). data remains valid until at least the next rising edge of k clock, approximately one full k clock cycle thereafter. regardless which read protocol is selected, read operations may be initiated consecutively, with no dead cycles between them. m1 m2 register - register l h register - flow thru l l register - latch h l reserved h h
4mb, sync lw, lvttl, rev 1.2 8 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary ? write operations these devices follow a late write protocol, where, during a write operation, data is provided to the sram one clock cycle after the address and control signals, eliminating the need for one of the bus- turnaround cycles required when changing from a read to a write operation. the late write function is controlled internally by using a dedicated one-deep write buffer to store the address and data signals as- sociated with the current write operation. the buffered data is not actually written to the memory array until the next write operation is initiated. when a write operation is initiated, all address and control signals (except g and zz) are latched into input registers on the rising edge of k clock. also at this time, any valid data currently stored in the one- deep write buffer (associated with the previous write operation) is written to the memory array. on the subsequent rising edge of k clock, the data and address signals for the current write operation are stored in the write buffer. this write pipeline mechanism allows write operations to be initiated consecutively, with no dead cycles between them. note: in order to maintain coherency, if a read operation is initiated to the same address as that of the last write operation (i.e. to the address of the write operation currently stored in the write buffer), read data is provided from the write buffer instead of the memory array. if only some of the bytes of data in the write buffer are valid, those bytes of data that are valid are provided from the write buffer, and those bytes of data that are invalid are provided from the memory array. ? sleep (power down) mode sleep (power down) mode is provided through the asynchronous input signal zz. when zz is asserted (high), the output drivers will go to a hi-z state, and the sram will begin to draw standby current. con- tents of the memory array will be preserved. an enable time (t zze ) must be met before the sram is guaranteed to be in sleep mode, and a recovery time (t zzr ) must be met before the sram can resume normal operation. ? power-up sequence power supplies must power up in the following sequence: v ss , v dd , v ddq , v ref , and inputs. v ddq must never exceed v dd .
4mb, sync lw, lvttl, rev 1.2 9 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary ? absolute maximum ratings (1) (1) stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions other than those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. ? pbga package thermal characteristics board size & thickness (board a, b): 7.62w x 11.43l x 1.57t (mm) item symbol rating unit supply voltage v dd -0.5 to +4.6 v output supply voltage v ddq -0.5 to +4.6 v input voltage v in -0.5 to v dd +0.5 (4.6v max.) v output voltage v out -0.5 to v ddq +0.5 (4.6v max.) v operating temperature t a 0 to 85 c junction temperature t j 0 to 110 c storage temperature t stg -55 to 150 c sample form ambient air flow (m/s) thermal resistance ( c/w) reference 1 q ja pkg only room temp 0 1 2 3 81.0 36.9 29.5 26.1 max thermal resistance 2 q ja pkg on board a* room temp 0 1 2 3 32.4 23.8 20.7 18.6 *board a is a two layer printed circuit board with very low density trace in both layers. 3 q ja pkg on board b** room temp 0 1 2 3 16.0 12.9 12.0 11.3 **board b is a four layer printed circuit board, same as board a except with two gnd planes in the middle layers. 4 q jc pkg only di water - 3.6 min thermal resistance
4mb, sync lw, lvttl, rev 1.2 10 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary ? dc recommended operating conditions ( v ss = 0v , t a = 0 to 85 o c) (1) v dd (max) up to 3.78v is supported. 3.47v is recommended for power consumption purposes only. (2) for v ddq = 2.5v or v ddq = 3.3v applications. (3) v ih (max) ac = v dd + 1.5v for pulse width less than 2.0 ns. (4) v il (min) ac = -1.5v for pulse width less than 2.0 ns. (5) these devices support three different input clocking schemes: a. lvttl differential - in this scheme, both clock inputs (k and k ) are driven differentially to the same voltage levels as the other inputs, i.e. from v ss to v ddq nominally. v kin , v dif , and v cm must all be considered when using this scheme. b. lvttl single ended - in this scheme, one of the two clock inputs (either k or k ) is driven to the same voltage levels as the other inputs, i.e. from v ss to v ddq nominally, while the other clock input (ei- ther k or k) is tied to an external reference voltage (v x ). v kin , v dif , and v x must all be considered when using this scheme. c. pecl differential - in this scheme, both clock inputs (k and k ) are driven differentially according to pecl guidelines. both v ih-pecl and v il-pecl must be considered when using this scheme. ? i/o capacitance (t a = 25 o c, f = 1 mhz) note: these parameters are sampled and are not 100% tested. item symbol min typ max unit supply voltage (1) v dd 3.13 3.3 3.47 v output supply voltage (2) v ddq 2.37 2.5, 3.3 3.47 v input high voltage (3) v ih 1.65 --- v dd + 0.3 v input low voltage (4) v il -0.3 --- 1.15 v clock (5) lvttl input signal voltage v kin -0.3 --- v dd + 0.3 v input dif ferential voltage v dif 0.5 --- v dd + 0.6 v input common mode voltage v cm 1.15 1.4 1.75 v input cross point voltage v x 1.15 1.4 1.75 v pecl input high voltage v ih-pecl 2.135 --- 2.420 v input low voltage v il-pecl 1.480 --- 1.825 v item symbol test conditions min max unit input capacitance c in v in = 0v --- 6 pf clock input capacitance c clk v in = 0v --- 6 pf output capacitance c out v out = 0v --- 7 pf
4mb, sync lw, lvttl, rev 1.2 11 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary ? dc electrical characteristics (v dd = 3.3v 5%, v ss = 0v, t a = 0 to 85 o c) 1. typical i dd values measured at v dd = 3.3v and t a = 25 o c, with a 75% read / 25% write operation distribution. item symbol test conditions min typ max unit input leakage current i li v in = v ss to v dd -1 --- 1 ua output leakage current i lo v out = v ss to v dd g = v ih -10 --- 10 ua power supply operating current - x36 i dd-5.0 i dd-4.5 i dd-4.0 i dd-3.6 i dd-3.3 i out = 0 ma ss = v il , zz = v il --- 665 695 725 755 785 --- ma power supply operating current - x18 i dd-5.0 i dd-4.5 i dd-4.0 i dd-3.6 i dd-3.3 i out = 0 ma ss = v il , zz = v il --- 595 625 655 685 715 --- ma power supply standby current i sb i out = 0 ma zz = v ih --- 60 --- ma output high voltage for v ddq = 3.3v v oh i oh = -6.0 ma 2.4 --- --- v output low voltage for v ddq = 3.3v v ol i ol = 6.0 ma --- --- 0.4 v output high voltage for v ddq = 2.5v v oh i oh = -6.0 ma 2.0 --- --- v output low voltage for v ddq = 2.5v v ol i ol = 6.0 ma --- --- 0.4 v
4mb, sync lw, lvttl, rev 1.2 12 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary ? ac electrical characteristics (register - register mode ) 1. all parameters are specified over the range t a = 0 to 85 o c. 2. these parameters are sampled and are not 100% tested. 3. these parameters are characterized but not 100% tested at 1.3ns. they are 100% tested at 1.5ns. item symbol -33 -37 -5 -6 unit min max min max min max min max cycle time t khkh 3.3 --- 3.6 --- 5.0 --- 6.0 --- ns clock high pulse width t khkl 1.3 *3 --- 1.3 *3 --- 1.5 --- 1.5 --- ns clock low pulse width t klkh 1.3 *3 --- 1.3 *3 --- 1.5 --- 1.5 --- ns address setup time t avkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns address hold time t khax 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns write enables setup time t wvkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns write enables hold time t khwx 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns synchronous select setup time t svkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns synchronous select hold time t khsx 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns data input setup time t dvkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns data input hold time t khdx 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns clock high to output valid t khqv --- 2.3 --- 2.4 --- 2.5 --- 2.5 ns clock high to output hold t khqx *2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns clock high to output low-z t khqx1 *2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns clock high to output high-z t khqz *2 --- 2.3 --- 2.4 --- 2.5 --- 2.5 ns output enable low to output valid t glqv --- 2.3 --- 2.4 --- 2.5 --- 2.5 ns output enable low to output low-z t glqx *2 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns output enable high to output high-z t ghqz *2 --- 2.3 --- 2.4 --- 2.5 --- 2.5 ns sleep mode enable time t zze *2 --- 20.0 --- 20.0 --- 20.0 --- 20.0 ns sleep mode recovery time t zzr *2 20.0 --- 20.0 --- 20.0 --- 20.0 --- ns
4mb, sync lw, lvttl, rev 1.2 13 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary ? ac electrical characteristics (register - latch & register - flow thru modes) 1. all parameters are specified over the range t a = 0 to 85 o c. 2. these parameters are sampled and are not 100% tested. 3. r-ft mode operation is verified functionally, but associated timing parameters are guaranteed by design only and are not 100 % tested. item symbol -33 -37 -5 -6 unit min max min max min max min max cycle time t khkh 5.0 --- 5.3 --- 5.3 --- 6.0 --- ns clock high pulse width t khkl 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns clock low pulse width t klkh 1.5 --- 1.5 --- 1.5 --- 1.5 --- ns address setup time t avkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns address hold time t khax 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns write enables setup time t wvkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns write enables hold time t khwx 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns synchronous select setup time t svkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns synchronous select hold time t khsx 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns data input setup time t dvkh 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns data input hold time t khdx 1.0 --- 1.0 --- 1.0 --- 1.0 --- ns clock high to output valid t khqv --- 5.0 --- 5.3 --- 5.3 --- 6.0 ns clock high to output hold (r-ft mode only) t khqx *2 2.0 --- 2.0 --- 2.0 --- 2.0 --- ns clock high to output low-z (r-ft mode only) t khqx1 *2 2.5 --- 2.5 --- 2.5 --- 2.5 --- ns clock low to output valid (r-l mode only) t klqv --- 2.3 --- 2.4 --- 2.5 --- 2.5 ns clock low to output hold (r-l mode only) t klqx *2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns clock low to output low-z (r-l mode only) t klqx1 *2 0.7 --- 0.7 --- 0.7 --- 0.7 --- ns clock high to output high-z t khqz *2 --- 2.3 --- 2.4 --- 2.5 --- 2.5 ns output enable low to output valid t glqv --- 2.3 --- 2.4 --- 2.5 --- 2.5 ns output enable low to output low-z t glqx *2 0.5 --- 0.5 --- 0.5 --- 0.5 --- ns output enable high to output high-z t ghqz *2 --- 2.3 --- 2.4 --- 2.5 --- 2.5 ns sleep mode enable time t zze *2 --- 20.0 --- 20.0 --- 20.0 --- 20.0 ns sleep mode recovery time t zzr *2 20.0 --- 20.0 --- 20.0 --- 20.0 --- ns
4mb, sync lw, lvttl, rev 1.2 14 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary ? ac test conditions (v ddq = 2.5v) (v dd = 3.3v 5%, v ddq = 2.5v -5%/+10%, t a = 0 to 85 c) item symbol conditions units notes input high level v ih 2.0 v t s 3 1.0ns input low level v il 0.8 v t s 3 1.0ns input rise & fall time 1.0 v/ns input reference level 1.4 v clock lvttl input high voltage v kih 2.2 v v dif 3 0.8v lvttl input low voltage v kil 0.6 v v dif 3 0.8v lvttl input common mode voltage v cm 1.4 v pecl input high voltage v ih-pecl 2.3 v pecl input low voltage v il-pecl 1.6 v clock input rise & fall time 1.0 v/ns clock input reference level k/k cross v output reference level 1.25 v output load conditions fig.1 dq 1.25 v fig. 1: ac test output load (v ddq = 2.5v) 50 w 50 w 5 pf 16.7 w 1.25 v 50 w 50 w 5 pf 16.7 w 16.7 w
4mb, sync lw, lvttl, rev 1.2 15 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary ? ac test conditions (v ddq = 3.3v) (v dd = v ddq = 3.3v 5%, t a = 0 to 85 c ) item symbol conditions units notes input high level v ih 2.4 v t s 3 1.0ns input low level v il 0.4 v t s 3 1.0ns input rise & fall time 1.0 v/ns input reference level 1.4 v clock lvttl input high voltage v kih 2.4 v v dif 3 1.0v lvttl input low voltage v kil 0.4 v v dif 3 1.0v lvttl input common mode voltage v cm 1.4 v pecl input high voltage v ih-pecl 2.3 v pecl input low voltage v il-pecl 1.6 v clock input rise & fall time 1.0 v/ns clock input reference level k/k cross v output reference level 1.4v v output load conditions fig.2 dq 1.4 v fig. 2: ac test output load (v ddq = 3.3v) 50 w 50 w 5 pf 16.7 w 1.4 v 50 w 50 w 5 pf 16.7 w 16.7 w
4mb, sync lw, lvttl, rev 1.2 16 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary timing diagram of write operations g ss sw /sbw x k n n+1 n+2 k sa dn dn+1 dq t khdx t dvkh dn-1 n+3 dn+2 t svkh t khsx t khqx1 t ghqz t glqv t glqx t khqv qn t khqz sw k k timing diagram of read and deselect operations n qn-1 n+2 sa g dq t wvkh t av k h t khwx t khax t khkh t khkl t klkh ss n+3 qn-2 t khqx register - register mode
4mb, sync lw, lvttl, rev 1.2 17 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary register - register mode sa ss g = v il timing diagram i of read-write-read operations ( ss controlled) k k n n+2 n+3 n+4 n+5 sw /sbw x read n deselect write n+2 read n+3 t khqz dq qn-1 qn dn+2 qn+3 read n+4 sa ss = v il g timing diagram ii of read-write-read operations ( g controlled) k k n n+2 n+3 n+4 n+5 sw /sbw x read n dummy write n+2 read n+3 t ghqz dq qn-1 qn dn+2 qn+3 read n+4 read
4mb, sync lw, lvttl, rev 1.2 18 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary register - latch mode t svkh t khsx t klqx1 t ghqz t glqv t glqx t klqv qn+1 t khqz sw k k timing diagram of read and deselect operations n qn n+1 sa g dq t wvkh t av k h t khwx t khax t khkh t khkl t klkh ss n+3 qn-1 t klqx t klqv t khqv timing diagram of write operations g ss sw /sbw x k n n+1 n+2 k sa dn dn+1 dq t khdx t dvkh dn-1 n+3 dn+2
4mb, sync lw, lvttl, rev 1.2 19 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary register - latch mode sa ss g = v il timing diagram of read-write-read operations k k n n+2 n+4 n+5 sw /sbw x read n write n+1 read n+2 deselect t khqz dq qn qn+2 dn+1 qn+4 read n+4 n+1 t khqz
4mb, sync lw, lvttl, rev 1.2 20 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary register - flow thru mode t svkh t khsx t ghqz t glqv t glqx qn+1 t khqz sw k k timing diagram of read and deselect operations n qn n+1 sa g dq t wvkh t av k h t khwx t khax t khkh t khkl t klkh ss n+3 qn-1 t khqx t khqv t khqx1 timing diagram of write operations g ss sw /sbw x k n n+1 n+2 k sa dn dn+1 dq t khdx t dvkh dn-1 n+3 dn+2
4mb, sync lw, lvttl, rev 1.2 21 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary register - flow thru mode sa ss g = v il timing diagram of read-write-read operations k k n n+2 n+4 n+5 sw /sbw x read n write n+1 read n+2 deselect t khqz dq qn qn+2 dn+1 qn+4 read n+4 n+1 t khqz
4mb, sync lw, lvttl, rev 1.2 22 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary test mode description functional description these devices provide a jtag boundary scan interface using a limited set of ieee std. 1149.1 functions. the test mode is intended to provide a mechanism for testing the interconnect between master (proces- sor, controller, etc.), srams, other components and the printed circuit board. in conformance with a subset of ieee std. 1149.1, these devices contain a tap controller, instruction register, boundary scan register and bypass register. jtag inputs/outputs are lvttl compatible only. test access port (tap) 4 pins as defined in the pin description table are used to perform jtag functions. the tdi input pin is used to scan test data serially into one of three registers (instruction register, boundary scan register and bypass register). tdo is the output pin used to scan test data serially out. the tdi pin sends the data into lsb of the selected register and the msb of the selected register feeds the data to tdo. the tms input pin controls the state transition of 16 state tap controller as specified in ieee std. 1149.1. inputs on tdi and tms are registered on the rising edge of tck clock. the output data on tdo is presented on the falling edge of tck. tdo driver is in active state only when tap controller is in shift-ir state or in shift-dr state. tck, tms, tdi must be tied low when jtag is not used. tap controller 16 state controller is implemented as specified in ieee std. 1149.1. the controller enters reset state in one of two ways: 1. power up. 2. apply a logic 1 on tms input pin on 5 consecutive tck rising edges. instruction register (3 bits) the jtag instruction register consists of a shift register stage and parallel output latch. the register is 3 bits wide and is encoded as follow: octal msb..........lsb instruction 0 0 0 0 bypass 1 0 0 1 idcode. read device id 2 0 1 0 sample-z. sample inputs and tri-state dqs 3 0 1 1 bypass 4 1 0 0 sample. sample inputs. 5 1 0 1 private. manufacturer use only. 6 1 1 0 bypass 7 1 1 1 bypass
4mb, sync lw, lvttl, rev 1.2 23 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary bypass register (1 bit) the bypass register is one bit wide and is connected electrically between tdi and tdo and provides the minimum length serial path between tdi and tdo. id registers (32 bits) the id register is 32 bits wide and is encoded as follows: boundary scan register (70 bits for 128kx36, 51 bits for 256kx18) the boundary scan register contains the following bits: k/k , c/c inputs are sampled through one differential stage and inverted internally to generate internal k/k , c/c signals for scan registers. place holders are required for some nc pins to allow for future den- sity upgrades, and are connected to v ss internally regardless of pin connection externally. device revision number (31:28) part number (27:12) sony id (11:1) start bit (0) 128k x 36 xxxx 0000 0000 0010 0001 0000 1110 001 1 256k x 18 xxxx 0000 0000 0010 0010 0000 1110 001 1 128k x 36 256k x 18 dq 36 dq 18 sa 17 sa 18 sw , sbw x5sw , sbw x3 ss , g 2ss , g 2 k, k , c, c 4k, k , c, c 4 zz 1 zz 1 m1, m2 2 m1, m2 2 place holder 3 place holder 3
4mb, sync lw, lvttl, rev 1.2 24 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary 128k x 36 scan order assignment (by exit sequence) note: nc pins at pad locations 6b (#34), 2b (#37), and 4d (#52) are connected to v ss internally, regardless of pin connection externally. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 5r 4p 4t 6r 5t 7t 6p 7p 6n 7n 6m 6l 7l 6k 7k 5l 4l 4k 4f 5g 7h 6h 7g 6g 6f 7e 6e 7d 6d 6a 6c 5c 5a 6b 5b m2 sa sa sa sa zz dqa dqa dqa dqa dqa dqa dqa dqa dqa sbw a k k g sbw b dqb dqb dqb dqb dqb dqb dqb dqb dqb sa sa sa sa nc sa sa nc sa sa sa sa dqc dqc dqc dqc dqc dqc dqc dqc dqc sbw c nc ss c c sw sbw d dqd dqd dqd dqd dqd dqd dqd dqd dqd sa sa sa m1 3b 2b 3a 3c 2c 2a 2d 1d 2e 1e 2f 2g 1g 2h 1h 3g 4d 4e 4g 4h 4m 3l 1k 2k 1l 2l 2m 1n 2n 1p 2p 3t 2r 4n 3r 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70
4mb, sync lw, lvttl, rev 1.2 25 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary 256k x 18 scan order assignment (by exit sequence) note: nc pins at pad locations 6b (#24), 2b (#27), and 4d (#37) are connected to v ss internally, regardless of pin connection externally. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 5r 6t 4p 6r 5t 7t 7p 6n 6l 7k 5l 4l 4k 4f 6h 7g 6f 7e 6d 6a 6c 5c 5a 6b 5b m2 sa sa sa sa zz dqa dqa dqa dqa sbw a k k g dqb dqb dqb dqb dqb sa sa sa sa nc sa sa nc sa sa sa sa dqb dqb dqb dqb sbw b nc ss c c sw dqb dqb dqb dqb dqb sa sa sa sa m1 3b 2b 3a 3c 2c 2a 1d 2e 2g 1h 3g 4d 4e 4g 4h 4m 2k 1l 2m 1n 2p 3t 2r 4n 2t 3r 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51
4mb, sync lw, lvttl, rev 1.2 26 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary ordering information. part number v dd size speed (cycle time / access time) r-r r-l & r-ft cxk77b3641a-33 3.3v 128k x 36 3.3ns / 2.3ns 5.0ns / 5.0ns cxk77b3641a-37 3.3v 128k x 36 3.6ns / 2.4ns 5.3ns / 5.3ns cxk77b3641a-5 3.3v 128k x 36 5.0ns / 2.5ns 5.3ns / 5.3ns cxk77b3641a-6 3.3v 128k x 36 6.0ns / 2.5ns 6.0ns / 6.0ns cxk77b1841a-33 3.3v 256k x 18 3.3ns / 2.3ns 5.0ns / 5.0ns cxk77b1841a-37 3.3v 256k x 18 3.6ns / 2.4ns 5.3ns / 5.3ns cxk77b1841a-5 3.3v 256k x 18 5.0ns / 2.5ns 5.3ns / 5.3ns cxk77b1841a-6 3.3v 256k x 18 6.0ns / 2.5ns 6.0ns / 6.0ns
4mb, sync lw, lvttl, rev 1.2 27 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary revision history rev. # rev. date description of modification rev 0.0 02/10/98 initial version rev 0.0 02/20/98 1. changed dc recommended operating conditions (p. 10). 2. added x36 and x18 typical i dd values (p. 11). 3. changed 2.5v v ddq ac test conditions (p. 14). 4. changed 3.3v v ddq ac test conditions (p. 15). 5. added x36 and x18 part numbers in boundary scan id registers (p. 23). rev 1.0 04/14/98 1. modified ac timing characteristics deleted -50 bin from all modes. renamed -36 bin to -33 bin in all modes. renamed -40 bin to -37 bin in all modes. renamed -45 bin to -4 bin in all modes. r-r mode: added clock pulse width timing parameters characterized but not 100% tested at 1.3ns note for -33 and -37 bins. -33 t khkh 3.6ns to 3.3ns t khqv , t khqz , t glqv , t ghqz 2.0ns to 2.3ns -37 t khkh 4.0ns to 3.6ns t khkl , t klkh 1.4ns to 1.3ns t khqv , t khqz , t glqv , t ghqz 2.1ns to 2.4ns -4 t khkh 4.5ns to 4.0ns t khqv , t khqz , t glqv , t ghqz 2.3ns to 2.5ns r-l, r-ft modes: added r-ft timing parameters guaranteed by design only note for all bins. removed t khqz1 from all bins. -33 t khkh 4.5ns to 5.0ns t khkl , t klkh 1.3ns to 1.5ns t khqv 5.5ns to 5.0ns t klqv , t khqz , t glqv , t ghqz 2.0ns to 2.3ns -37 t khkh 4.5ns to 5.5ns t khkl , t klkh 1.4ns to 1.5ns t klqv , t khqz , t glqv , t ghqz 2.1ns to 2.4ns -4 t khkh 5.0ns to 5.7ns t khqv 6.0ns to 5.7ns t klqv , t khqz , t glqv , t ghqz 2.3ns to 2.5ns 2. added 3.78v v dd (max) support note to dc recommended operating conditions (p. 10). 3. changed all maximum ambient temperature references (t a max) from 70 o c to 85 o c (pp. 9-15).
4mb, sync lw, lvttl, rev 1.2 28 / 28 september 24, 1998 sony ? cxk77b3641agb / CXK77B1841AGB preliminary rev 1.1 05/01/98 1. modified ac timing characteristics added -6 bin to all modes. 2. added x36 and x18 typical power supply operating current for 3.3ns cycle time (i dd-3.3 ) to dc electrical characteristics (p. 11). rev 1.2 09/24/98 1. modified ac timing characteristics renamed -4 bin to -5 bin in all modes. r-r mode: -5 t khkh 4.0ns to 5.0ns r-l, r-ft modes: -37 t khkh 5.5ns to 5.3ns t khqv 5.5ns to 5.3ns -5 t khkh 5.7ns to 5.3ns t khqv 5.7ns to 5.3ns rev. # rev. date description of modification

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